1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same.
2. Description of the Related Art
In conventional DRAM (Dynamic Random Access Memory) of the STC (Stacked Capacitor Cell) type, a capacitor has been made to have a three-dimensional structure, thus having an increased surface area in the height direction, in order to compensate for a decrease in the electric capacitance of the capacitor with miniaturization. The capacitor accordingly has a section with an increased aspect ratio and the device structure is complicated. Thus, it has been difficult to fabricate the device and to ensure both of a required capacitance and a satisfactory yield compatibly. An exemplary conventional capacitor structure is disclosed in Japanese Patent Laid-Open No. 2004-71759.
On the other hand, the number of interconnection layers is increasing as the capability and the performance of a semiconductor device become higher. When a multi-level interconnection structure is formed after the formation of a capacitor extended in the height direction, the yield tends to lower. Also, this manner of forming such a multi-level interconnection structure results in the addition of a process dedicated to the formation of memory cells to the logic formation process in the fabrication of a logic device with embedded DRAM. Thus, an increase in cost relative to the basic process cost and a decrease in yield are unavoidable.
In a sectional structure of conventional DRAM as shown in FIG. 11A and FIG. 11B, a capacitor element is formed in a memory cell region (shown in FIG. 11A) to effectively utilize the space thereof, whereas only a through-hole and a via plug filling the through-hole are present in a layered region of a peripheral circuit region (FIG. 11B) corresponding to a capacitor element forming region of the memory cell region and, hence, space utilization efficiency is low.
As described above, the capacitor element of DRAM needs to have a capacitor structure which is enlarged in the height direction in order to ensure a required storage capacitance, as the storage capacitance becomes insufficient with miniaturization. Accordingly, the proportion of the region in which only the through-hole extends has increased in the peripheral circuit region generation by generation, which forms a factor in lowering the performance of the basic device, such as an increase in through-hole resistance.
Since a signal line and other interconnection wires including a source line cannot extend through the capacitor region of a conventional memory cell, the formation of interconnection wires have to be conducted independently after the completion of the capacitor. For this reason, it is difficult to provide the peripheral circuit with a necessary and sufficient number of interconnection layers. Thus, the performance of the peripheral circuit cannot sufficiently be improved.
In addition, separate formations of the capacitor and the interconnection wires constitute a cost increasing factor.
For the reasons stated above, it is difficult to realize a logic LSI with a large-capacity embedded DRAM at a low cost.